[05-17]ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration

文章来源:  |  发布时间:2023-05-10  |  【打印】 【关闭

Title: ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration
Speaker: 石侃博士(中科院计算所副研究员)
Time: 10:00am, May 17 (Wednesday), 2023.
Venue: 线下:中科院软件园区5号楼3层计算机科学国家重点实验室报告厅(334房间)
Verification typically consumes the majority of the time in the hardware development cycle. Primarily this is because multiple iterations to debug hardware using software simulation is extremely time-consuming. While FPGAs can be utilised to accelerate the simulation, existing methods either provide limited visibility of design details, or are expensive to check against a reference model dynamically at the system level.
In this talk, I will present ENCORE, an FPGA-accelerated framework for processor architecture verification. The design-under-test (DUT) hardware and the corresponding software emulator run simultaneously on the same FPGA with hardened processors. EN- CORE embodies hardware modules that dynamically monitor and compare key registers from both the DUT and reference model, pausing the execution if any mismatches are detected. In this case, ENCORE automatically creates snapshots of the current design status, and offloads this to software simulators for further debugging. We demonstrate the performance of ENCORE by running RISC-V processor designs and benchmarks. We show that ENCORE can achieve over 44000× speedup over a traditional software simulation-based approach, while maintaining full visibility and debugging capabilities.
石侃博士,中科院计算所先进计算系统研究中心副研究员,B站知名 UP主“老石谈芯”,主要研究方向:敏捷芯片设计与验证,FPGA,云数据中心体系结构。博士毕业于伦敦帝国理工学院,曾任英特尔英国研发中心资深芯片设计工程师,兼任英特尔研究院研究科学家。曾获MICRO Top-Picks论文奖,两次获得HiPEAC论文奖,一次最佳论文提名。RISC-V国际基金会技术委员会委员,国际开源硬件组织OpenHW亚洲工作组常委。了解石侃博士的更多信息请访问https://shilicon.github.io/